FIG. 1 represents an example of an EEPROM memory 10 comprising memory cells, with each memory cell comprising a floating gate transistor and a MOS type access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory 10 further includes means for respectively applying during the erasing phases of the memory cells a first electrical voltage and a second electrical voltage on the control gate and on the second terminal of the floating gate transistors of the memory cells to be erased.
The memory 10 comprises memory cells CEi,j connected to lines for selecting a word line WLSLi and to bit lines BLj. The bit lines are grouped in columns COLk comprising M bit lines BL0 to BLM-1. The memory cells connected to a same selection line WLSLi form a word line WLi. The memory cells of a same word line WLi connected to M bit lines of a column COLk form a memory word Wi,k providing storage for M bits. For the sake of simplicity, a single word Wi,k belonging to a column COLk and to a word line WLi is illustrated in FIG. 1.
Each memory cell CEi,j comprises a floating gate transistor FGT and an access transistor AT of the MOS type. Transistor AT has its gate connected to line WLSLi, its drain D is connected to a bit line BLj and its source S is connected to the drain D of the FGT transistor. Transistor FGT has its control gate G connected to a gate control line CGLk, and its source S connected to a source line SL. The source line SL is connected to ground via a SLT transistor driven by a signal SLS. The CGLk line is connected to a line for selecting a column CLk via a gate control transistor CGTk, with its gate connected to line WLSLi.
Each WLSLi line is controlled by a signal VWL delivered by an output OUTi of a line decoder RDEC. Each CLk line is controlled by a gate control signal VCG delivered by a column latch LTk, and each latch LTk is controlled by a column selection signal SCOLk delivered by an output OUTk of a column decoder CDEC. Decoders RDEC and CDEC respectively receive the most significant bits ADH and the least significant bits ADL of the address of the word Wi,k to be selected.
Each bit line BLj is connected to a programming latch LPj driven by a column selection signal SCOLk. Each latch LPj is connected to a bus WB for receiving, before a programming operation, one data bit Bj from M bits, b0 to bM-1. Each bit line BLj is also connected to a readout amplifier SAj via a column selection transistor TSk, a readout transistor TR and a multiplexing bus MB. Transistors TSk are driven by the column selection signal SCOLk whereas the readout transistors TR are driven by a readout signal READ. The M bits of a word Wi,k may be read by readout amplifiers, SA0 to SAM-1, connected at the input to the multiplexing bus MB and at the output to the bus RB.
In such a memory, a memory cell erasing or programming operation includes injecting or extracting electrical charges by the tunnel effect (Fowler Nordheim effect) in/from the floating gate of the FGT transistors. An erased FGT transistor has a threshold voltage VT1, and a programmed FGT transistor has a threshold voltage VT2. When a readout voltage Vread between VT1 and VT2 is applied on its control gate, an erased FGT transistor remains blocked which conventionally corresponds to a logic 1, and a programmed transistor is conducting which conventionally corresponds to a logic 0. A reverse convention may also be used.
The collective erasing of the FGT transistors of a word line WLi is obtained by applying a voltage Vpp from 15 to 20 V on the control gate of the FGT transistors, while the source line SL is set to 0 and the drain of the FGT transistors is at a floating potential. Individual programming of the FGT transistors is achieved by applying the voltage Vpp on the drains of the FGT transistors via the access transistors AT, while the control gate of the FGT transistors is set to 0 and the source line SL is at a floating potential. These operations are achieved by decoders RDEC, CDEC and latches LCk, LPj by having the supply voltage Vcc of these components increase 3 to 5V to the voltage Vpp.
TABLE 1 summarizes the values of the control signals during the erasing, programming and readout operations for a memory cell CEi,j. VS is the control signal present on the source line SL, VBL is the control signal present on the bit line BLj and Vsense is a signal delivered by the readout amplifiers.
TABLE 1OperationControl signals ERASINGPROGRAMMINGREADOUTVCGVpp0 (ground)VreadVWLVppVppVccVS0 (ground)floating0 (ground)VBLfloatingVppVsense
Because the voltage Vpp is applied on their gate or on their drain, the access transistors AT and the floating gate transistors FGT are subject to a significant electrical stress during the successive erasing/programming cycles. The gate oxide of these transistors are selected accordingly, and these are high voltage oxides assumed capable of withstanding voltages which may attain 30 V. However, these gate oxides are not perfect and have various defects or impurities which may cause their breakdown in normal conditions of use. Thus, the breakdown of an access transistor or a floating gate transistor is occasionally observed after a few hundred or thousand erasing/programming cycles. Although the breakdown probability for a transistor is low, the number of memory cells present in an EEPROM memory is high, and statistically, the rejection rate of faulty memories is not insignificant.
To overcome this drawback, it is known how to associate an error correction code or ECC code with data bits stored in the memory, allowing at least one erroneous bit to be detected and corrected in a string of bits. For example, by adding a 4 bit Hamming code to 8 data bits, an erroneous bit may be detected and corrected upon reading the string of bits. This precaution is found to be generally sufficient for correcting the consequences of the breakdown of a floating gate transistor, but is found to be inefficient for countering a fault of an access transistor. However, it is often impossible to properly erase the memory cells of a word line WLi comprising a faulty access transistor or to properly program memory cells connected to a bit line BLj comprising a faulty access transistor.
As it will be explained in detail below, these drawbacks are attributable to the existence of a short-circuit between the gate and the drain or the source of the access transistor, which causes the voltage Vpp to drop on the line for selecting the word line during an erasing cycle or which causes the voltage Vpp to drop on the bit line during a programming cycle.